With continuous development of electronic integration technologies, an operating frequency of a chip is higher, and a stricter requirement is imposed on a time sequence relationship between signals. For signals transmitted at a high speed, for example, double data rate (DDR) signals, a time sequence relationship directly affects signal quality. If an input time sequence deviation of a chip on a board exceeds a design standard, an input instruction may not be executed. To ensure that the chip can work stably, a time sequence deviation between signals must be as small as possible. This requires that a circuit designed by chip designers should not only implement basic functions, but also perform time sequence control on signals properly if possible. Transmission of the signals on a package substrate and a printed circuit board (PCB) may cause a time sequence deviation. A length deviation of a signal transmission cable is an important factor that affects a time sequence. This requires that total lengths of cables, on the substrate and the PCB, of signals on which time sequence control needs to be performed should be as equal as possible, so that a time sequence deviation between the signals is minimized. Therefore, if a simple and high-efficiency method can be used to implement control on a signal time sequence on the package substrate, not only difficulties in chip design and layout and chip costs can be reduced, but also signal quality of a chip and competitiveness of the chip can be improved.
In view of this, a general manner in the prior art is to wind, on the substrate and the PCB, all circuit board cables that require time sequence control, so that the cables have equal lengths on the substrate and have equal lengths on the PCB, thereby achieving a same total length of a whole link, and further reducing the time sequence deviation between the signals. As shown in FIG. 1, a chip includes a die 11 and a substrate 14. The die and the substrate of the chip are wrapped together by using a packaging process. Herein, for ease of description, the substrate and the die are marked separately. Conductive bumps on a lower surface of the die 11 are connected to the substrate 14 fixedly by using solder balls 12. The substrate 14 is fixed on a PCB 17 by using solder balls 15. For visual description, three cables 13 are marked in the substrate, and three circuit board cables 19 are also laid out in the printed circuit broad 17. The three circuit board cables 19 correspond to the three substrate cables 13 in a one-to-one manner, to form three signal paths. As can be clearly seen from FIG. 1, to wind the three cables 13 into equal lengths on the substrate and reduce a time sequence deviation between the three signal paths, two of the cables 13 both include a serpentine cable 18 to prolong lengths of the two cables, likewise, two of the cables 19 also include a serpentine cable 16. In a disposing manner shown in FIG. 1, a large amount of cable winding space needs to be reserved on both the substrate 14 and the printed circuit broad 17 of the chip. Especially the cable winding space is limited because a size of the substrate 14 is small. Therefore, more cable layers may be required to implement equal-length control of signal cables. This may cause an increase of substrate layers, and is disadvantageous for chip cost control. In addition, an electronic device manufacturer needs to obtain, by various means, a delay of each path on the chip and the printed circuit board, and lay out a cable separately for each path, which increases production and design costs of an electronic device greatly.